A basic metallized ceramic (MC) substrate process known in the art begins with a ceramic square, on the top surface of which, metallurgical strata of chromium for adhesion, copper for conduction, and chromium for a solder flow barrier, are deposited. A pattern of conductors is defined in the strata by a photolithographic process using standard photoresist techniques and sequential etching methods. The pattern forms wiring that will subsequently connect semiconductor chip input/output (I/O) solder bumps to the I/O pins attached to the MC substrate. The pins provide electrical and mechanical connections with the outside world. The pins are typically inserted through preformed via-holes in the substrate and are mechanically swaged in place to form a bulge. Preformed via-holes are disposed in an array which may have various patterns. The ends of the conductors at those points where pins are provided take the form of eyelets. The heads of connecting pins previously inserted in the substrate are bonded to the eyelets of conductors formed on the top surface simultaneously with the bonding of the semiconductor chip to the conductors.
The preferred method of bonding the head of connecting pins comprises the steps of: applying a droplet of flux to the head of the pin, then applying a solder ball to the head where it is held in position because of the adhesive capacity of the flux, heating in a furnace containing a nitrogen atmosphere to cause a solder reflow and cooling to enable the solder to solidify. The method is described in detail in U.S. Pat. No. 4,462,534 entitled, "Method of Bonding Connecting Pins to the Eyelets of Conductors Formed on a Ceramic Substrate", by A. Bitaillou et al and assigned to the same assignee of the present invention.
The chips are attached to the substrate using the "Controlled Collapse Chip Connection" (C-4) process developed for tin-lead interconnections, also known under the generic name of "Flip Chip" technique. A polyimide coating is applied to the top surface, an aluminum cap is placed over the assembly, and an epoxy sealant is dispensed on the underside as a liquid and cured to provide a "quasi-hermetic" seal. After it has been marked and tested, the completed module is then ready for attachment to the appropriate second level package, such as a PCB.
Metallized ceramic (MC) technology as described above is a simplified version of the well known multilayer ceramic (MLC) technology. Compared to the MLC technology which appears to be only appropriate for use in medium and high performance computers, the MC technology aims preferably at more specific applications such as various peripherals, including banking machines, personal computers, etc. where low cost and simplicity are a required.
One of the problems associated with MC technology is related to the use of the aforementioned pins. These pins are elongated in shape and require perforated PCB's, i.e., PCB's provided with plated via-holes to receive the pins before bonding. Their handling, and automatic insertion into the plated via-holes still remain a problem and are a serious detractor from manufacturing yields.
In addition, perforated PCB's are costly and much space is lost due to the presence of the plated via-holes to receive the corresponding pins. Generally, the diameter of the elongated pins before tinning is about 0.6 mm, while the plated via-holes in the PCB have a diameter of about 1 mm. Due to the internal construction of the PCB, it is almost impossible to reduce the standard center to center distance of 2.54 mm. Should the use of pins be avoided, perforated PCB's would no longer be necessary and increased density could be reached because the center to center distance could be reduced to less than 1.27 mm., therefore considerably increasing the number of I/O's permitted on the same surface of the PCB. Furthermore, as the number of pins increases, the operation of inserting the module into the PCB becomes more difficult, and the likelihood of having pins bent during this step increases too. Moreover, when pins are used as I/O's, the module comes into close contact with the PCB leaving no clearance between them, unless costly stand-offs are provided to the pins. As a result, the cooling of the module is made more difficult. Another problem is that the use of modules having pins as I/O's in combination with perforated PCB's prevents bonding of MC modules on both sides of the PCB's. Still, another problem raised by the use of such a great number of pins is the difficulty of reworking the module to make engineering changes.
Today's packaging techniques are evolving towards the extensive usage of surface mount techniques (SMT) in order to improve the density of circuits at the card level and reduce packaging costs. According to SMT technology, perforated PCB's are no longer used and the terminals of modules are directly bonded to the desired metal lands of the PCB.
Commonly used surface mount modules such as those mentioned above are provided with peripheral I/O's. In this case the I/O's consist of metal leads bent under the bottom surface of the module that come into contact with the metal lands formed at the surface of the PCB. The cost of these modules becomes rapidly prohibitive when the number of I/O's increases to a high count (typically: 100 to 300) because of the amount of area required. For example, for a given technology, doubling the number of pins leads to a four-fold increase in module area with a similar loss of card area, and a degradation of the module electrical characteristics (inductances, resistances) which in turn, results in parasitic effects.
On the contrary, a module with I/O's placed on a grid pattern would be more efficient in terms of handling large numbers of I/O's. For example, an increase of I/O count by a factor of two, will result in a more reasonable factor of two for the module area. The system designer would then be able to take full advantage of the card density and optimization, and thus cost as well as the resulting electrical performance would be significantly improved. As a matter of fact, a pinless module having I/O'placed according to a grid pattern at the center of the bottom surface (opposite to said top surface) of the substrate or even occupying the whole bottom surface, would be a highly desirable solution in all respects.
An attempt to provide a pinless MC module is described in the IBM Technical Disclosure Bulletin, Vol. 20, No. 10, March 1978, page 3872, in an article entitled, "Pinless Module Connector" by E. Stephans. An electronic package is shown which includes a printed-circuit card, a metallized ceramic (MC) substrate, and an integrated circuit chip attached thereon. In this package, the integrated circuit chip is connected to the MC substrate by small solder joints in a standard way. The solder joints are usually spherical and have a diameter in the order of 0.1 mm. Unlike the conventional connection between the MC substrate and the PCB by elongated pins, the MC substrate is connected to the PCB by copper balls. These balls are approximately 1.5 mm in diameter. The package can be fabricated by attaching the copper balls to the MC substrate with conductive epoxy which fills the preformed via holes of the MC substrate. After the copper balls are attached to the MC substrate, the latter is placed on the PCB. The copper balls are then surface soldered to the metal lands formed on the top surface of the PCB.
The described solution, although resulting in a pinless MC module appears to present some drawbacks and insufficiencies. The technique of filling the preformed via-holes of the MC substrate is not detailed. Moreover, conductive epoxy is known to be a relatively high resistive material, therefore, the quality of the electrical connection between the conductive epoxy and the metallization pattern formed onto the top surface of the MC substrate is questionable.
In addition, the sticking of the copper balls to the conductive epoxy raises some unsolved problems, in particular the alignment of the ball with the via-hole and the reliability of the composite bond between the epoxy and the ball is not assessed. Furthermore, the possibility of reducing the copper ball size is questionable. The behavior of this composite bond during thermal stresses caused by the different expansion coefficients between the MC substrate and the PCB, has not been addressed either.
Therefore, there still exists a need for a method of forming pinless MC modules having I/O's on the bottom surface which obviates all of the problems cited above.